Example embodiments relate to semiconductor devices, and more particularly to semiconductor devices adopting design-for-test (DFT) schemes, and semiconductor modules and test systems including such semiconductor devices.
Semiconductor devices generally include input/output (I/O) terminals to transmit and receive signals through transmission lines that are coupled to an external device. An impedance of the I/O terminal should be sufficiently matched to an impedance of the transmission line in order to reduce and/or prevent signal reflections at the interface between the semiconductor device and the transmission line. However, as the operating speed of semiconductor devices has increased, it has become more difficult to match the impedance of an I/O terminal to the impedance of an associated transmission line, and the signals transmitted over the transmission lines may be distorted due to such impedance mismatching.
Various impedance matching methods have been developed to match the impedance of an I/O terminal to the impedance of an associated transmission line. For example, some semiconductor memory devices such as the Double Data Rate 3 (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) devices perform the impedance matching by using a ZQ calibration unit and a ZQ terminal included in the semiconductor memory device and an external ZQ resistor connected between the ZQ terminal and a ground voltage.